I. Field of the Disclosure
The technology of the disclosure relates generally to cache management in multicore processor-based systems, and, in particular, to reallocating caches among processor cores.
II. Background
Modern computer processor architectures frequently make use of multicore processors, which are computing elements that include two or more “cores,” or processing units. Some computer processor architectures, such as those used for low-power mobile applications, provide a separate processor core power domain for each processor core of a multicore processor. In this manner, all elements of each processor core can be powered by the same power and ground supply. Such multicore processors often also provide shared caches that are accessible by all processor cores. Because access to the shared caches must be arbitrated among the processor cores, the use of shared caches by multicore processors may result in increased cache access latency.
To mitigate the effects of arbitration latency, the processor core power domain for each processor core of a multicore processor often includes a private cache (e.g., a Level 2 (L2) cache, as a non-limiting example) that is accessible only by that processor core. For example, in an eight-core processor, each of the eight processor cores is associated with its own power domain and its own private cache. The use of private caches improves arbitration latency, which improves overall processor and system performance.
However, when a processor core of a multicore processor is placed in a “power-collapsed” or shutdown state (e.g., in the course of conventional power management), the corresponding private cache residing in a same power domain becomes unavailable for use, and thus does not contribute to performance improvement. For example, benchmark applications used to measure processor performance typically employ between one and four processor cores. Consequently, in an eight-core processor, between four and seven of the available processor cores may be placed in a power-collapsed state. This renders the corresponding private caches unavailable for use, resulting in decreased processor performance and possibly inaccurate benchmark results.